Field-programmable devices are popular in the electronics industry because they provide the user with great flexibility in tailoring a general integrated circuit to meet specific applications at low cost. The most common type of programmable element used in a field-programmable integrated circuit such as a field-programmable logic device ("PLD") is a fusible link or fuse. Programming involves destroying (or "blowing") a specific pattern of fuses to create an open circuit at each location where a connection is not wanted. A closed circuit exists at each location where a fuse remains intact to provide an electrical connection. Another type of programmable element is the so-called "antifuse". In contrast to a fuse, an antifuse is initially an open circuit and is programmed to create a closed circuit.
FIG. 1 illustrates a segment of a two-level PLD, such as the PLSlOO integrated circuit made by Signetics Corp., in which an array of programmable AND gates drives an array of programmable OR gates. The AND array operates on M array input signals V.sub.I1 -V.sub.IM supplied on M array input lines L.sub.I1 -L.sub.IM. The OR array consists of N OR gates that respectively provide N array output signals on N array output lines L.sub.O1 -L.sub.ON.
The two programmable arrays are arranged in a number of columns. The circuitry centering about a typical column 10 is shown in FIG. 1. Column 10 consists of lines L.sub.U and L.sub.L coupled together through a low-value resistor R.sub.C. Gate X of the AND array is connected to line L.sub.U. Portions of all N OR gates are connected to line L.sub.L. These portions are collectively referred to as circuit Y. A current supply consisting of a resistor R.sub.S1 connected to a source of a high supply voltage V.sub.CC provides line L.sub.U with current for normal operation. This current is insufficient to cause any of the programmable elements along column 10 to be programmed.
AND gate X has M input sections that respectively receive voltages V.sub.I1 -V.sub.IM. Letting j be a running integer, each input section consists of a fuse F.sub.Xj connected in series with a Schottky diode D.sub.Xj between lines L.sub.Ij and L.sub.U. The output signal from gate X is supplied as a column signal on line L.sub.U through resistor R.sub.C to line L.sub.L.
The column signal is an input signal to all N OR gates. In particular, one of the input sections of each OR gate receives the column signal. Letting k be a running integer, each OR input section shown in FIG. 1 consists of a fuse F.sub.Yk connected in series with the base-emitter junction of an NPN transistor Q.sub.Yk between lines L.sub.L and L.sub.Ok. The Q.sub.Yk collectors are coupled through a diode D.sub.C to the V.sub.CC supply. The other input sections of the OR gates are connected to the other columns in the same way.
The foregoing components are utilized during normal PLD switching. The R.sub.S1 supply provides column current for gate X and charges the column capacitance--i.e., parasitic capacitance portions C.sub.PU and C.sub.PL respectively associated with lines L.sub.U and L.sub.L. The R.sub.S1 supply also provides drive current for circuit Y.
Additional circuitry is needed to program the AND and OR circuit elements. The main item of programming circuitry is a column select circuit 12 which selects one of the columns in response to select signals V.sub.S. Column select 12 is connected between line L.sub.U and a source of a programming voltage V.sub.PP. The Q.sub.Yk collectors are also connected to the V.sub.PP supply via a diode string D.sub.PP.
In programming the circuitry of FIG. 1, line L.sub.Ij or L.sub.Ok of a fuse F.sub.Ij or F.sub.Ok to be destroyed is set at a low voltage. The remainder of lines L.sub.I1 -L.sub.IM and L.sub.O1 -L.sub.ON are allowed to float. Column 10 is then selected. During a programming period, voltage V.sub.PP is raised from circuit ground to a value considerably higher than V.sub.CC. Circuit 12 then provides line L.sub.U with current at a very high voltage. If line L.sub.Ij is the line set at a low voltage, diode D.sub.Xj turns on very hard and draws sufficient current to blow fuse F.sub.Xj. If line L.sub.Ok is low, transistor Q.sub.Yk similarly turns on hard. It draws enough current through diode string D.sub.PP to blow fuse F.sub.Yk.
An advantage of the PLD of FIG. 1 is that circuit 12 is utilized in selecting columns to program both the AND array and the OR array. It is not necessary to have separate select circuits for the two arrays. This keeps the component count down. Another advantage is that very little voltage drop occurs between the arrays during normal switching (or AC) operation, thereby allowing voltages V.sub.O1 -V.sub.ON to attain relatively high levels.
The necessity to charge the column capacitance with current from the R.sub.S1 supply does, however, limit the switching speed. Future applications entailing more gates will require more current to drive the extra gates and to charge the attendant additional column capacitance. Faster switching speed will often be needed. Due to power limitations on the circuitry that drives signals V.sub.I1 -V.sub.IM, providing the additional current from the R.sub.S1 supply is inefficient. It would be desirable to have a technique for increasing the L.sub.L current to achieve faster switching and/or to accommodate more gates without necessarily increasing the L.sub.U current and without sacrificing the aforementioned advantages.